The present invention relates, in general, to semiconductor devices, and more particularly, to a novel method of testing a semiconductor device.
In the past, the semiconductor industry has utilized input protection networks to prevent damage to high impedance electrodes of semiconductor devices such as the gate electrode of metal oxide semiconductor (MOS) transistors. These input protection networks generally are used to minimize the amount of damage caused by electro-static discharge to the gate electrode.
Although the input protection network prevents damage, it also presents a problem while testing the MOS transistor's gate oxide rupture voltage. Such testing is often referred to as determining the gate oxide integrity, or testing the gate oxide. During testing, the input protection network typically functions as a voltage clamp that limits the maximum voltage that can be applied to the transistor's gate. Since the voltage required to test the gate oxide rupture voltage is typically higher than the clamp voltage, the input protection network prevents accurate testing of the gate oxide rupture voltage.
Accordingly, it is desirable to have a method of testing a semiconductor device that is not limited by the device's internal circuitry.